/* Check that

(define_expand "incscc"
  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
        (plus:SI (match_operator:SI 2 "arm_comparison_operator"
                    [(match_operand:CC 3 "cc_register" "") (const_int 0)])
                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
  "TARGET_32BIT"
  ""
)

(define_insn "*arm_incscc"
  [(set (match_operand:SI 0 "s_register_operand" "=r,r")
        (plus:SI (match_operator:SI 2 "arm_comparison_operator"
                    [(match_operand:CC 3 "cc_register" "") (const_int 0)])
                 (match_operand:SI 1 "s_register_operand" "0,?r")))]
  "TARGET_ARM"
  "@
  add%d2\\t%0, %1, #1
  mov%D2\\t%0, %1\;add%d2\\t%0, %1, #1"
  [(set_attr "conds" "use")
   (set_attr "length" "4,8")]
)

works when the condition code is the result of a maverick comparison.

Before removing ltgt and uneq from maverick_comparison_operators this would
generate an ICE at all optimization levels:
	incscc.c:38: error: unrecognizable insn:
	(insn 18 17 19 3 incscc.c:36 (set (reg:SI 146)
		(uneq:SI (reg:CCMAV 24 cc)
		    (const_int 0 [0x0]))) -1 (nil))
because define_cond_exec with maverick_comparison_operator would generate
these two conditions that then do not match arm_comparison_operator in the
incscc rules.
*/

foo(int i, double a, double b, double c)
{
	if (__builtin_isunordered(a,b)) i++;
	if (!__builtin_isunordered(b,c)) i++;
	return(i);
}